A continuing goal of integrated circuit fabrication is to decrease the dimensions thereof. Integrated circuit dimensions can be decreased by reducing the dimensions and spacing of the constituent features or structures. For example, by decreasing the dimensions and spacing of features (e.g., storage capacitors, access transistors, access lines) of a memory device, the overall dimensions of the memory device may be decreased while maintaining or increasing the storage capacity of the memory device.
As the dimensions and spacing of semiconductor device features become smaller, conventional lithographic processes become increasingly more difficult and expensive to conduct. Therefore, significant challenges are encountered in the fabrication of nanostructures, particularly structures having a feature dimension (e.g., critical dimension) of less than a resolution limit of conventional photolithography techniques (about 50 nm). It is possible to fabricate semiconductor structures of such feature dimensions using a conventional lithographic process, such as shadow mask lithography and e-beam lithography. However, use of such processes is limited because the exposure tools are extremely expensive or extremely slow and, further, may not be amenable to formation of structures having dimensions of less than 50 nm.
The development of new lithographic processes, as well as materials useful in such processes, is of increasing importance to make the fabrication of small-scale devices easier, less expensive, and more versatile. One example of a method of fabricating small-scale devices that addresses some of the drawbacks of conventional lithographic techniques is self-assembled block copolymer lithography.
In self-assembled block copolymer lithography, block copolymer materials formed on a substrate are subject to microphase segregation, such as by annealing, to self-assemble the block copolymer materials into ordered nano-scale domains of one block of the block copolymer materials in a matrix of the other block of the block copolymer materials. Then, the domains of one block in the self-assembled block copolymer materials may be selectively removed, leaving the domains of the other block as an etch mask on the substrate. Dimensions of the self-assembled domains so formed are conventionally in the range of 5 nm to 50 nm, which are the dimensions that are extremely difficult to define using conventional lithographic techniques. Therefore, self-assembled block copolymer materials are useful as an etch mask in fabrication of nano-scale semiconductor devices.
Although the self-assembled block copolymer lithography is useful for fabrication of semiconductor structures having dimensions of less than 50 nm, there are still problems that must be addressed. Self-assembled block copolymer structures including the self-assembled block copolymer materials may not provide nano-scale etch masks with sufficient pattern fidelity in terms of line edge and roughness. For example, the self-assembled block copolymer structures often include undesirable random curvatures at the interfaces of domains, resulting in nano-scale etch masks having undesirably high degree of edge roughness and inconsistent widths. One conventional approach to address this problem is by removing (i.e., cutting, chopping) the portions of self-assembled block copolymer domains having undesirable random curvations, prior to further processing the self-assembled block copolymer structures into nano-scale etch masks.
Additionally, the different domains of the self-assembling block copolymer structures often have little or no etch selectivity from one another. Therefore, improving etch selectivity of the self-assembled domains is desirable.
Accordingly, there is a need for more reliable and less expensive fabrication techniques which are suitable for fabricating complex devices with the desired enhanced density to meet future demands.